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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20AKT is a 4-bank x 16777216-word x 4-bit, M2V56S30AKT is a 4-bank x 8388608-word x 8-bit, M2V56S40AKT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40 AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v0.3V power supply - Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - LVTTL Interface - 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch
Max. Frequency @CL2 M2V56S20/30/40 AKT -5 M2V56S20/30/40 AKT -6 M2V56S20/30/40 AKT -7 133 MHz 100MHz 100 MHz Max. Frequency @CL3 166 MHz 133 MHz 100MHz
Standard PC133 (CL2) PC133 (CL3) PC100 (CL2)
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM x4 x8 x16
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC NC NC VDD NC LDQM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC NC NC NC VSS UDQM NC CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC NC NC NC VSS DQM NC CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC NC NC NC VSS DQM NC CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
CLK CKE /CS /RAS /CAS /WE DQ0-15 DQM, DQMU/L A0-12 BA0,1 Vdd VddQ Vss VssQ
: : : : : : : : : : : : : :
Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O Output Disable / Write Mask Address Input Bank Address Input Power Supply Power Supply for Output Ground Ground for Output
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
BLOCK DIAGRAM
I/O Buffer
Memory Array Bank #0
Memory Array Bank #1
Memory Array Bank #2
Memory Array Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer A0-12 BA0,1 CLK CKE
Control Signal Buffer
/CS /RAS /CAS /WE DQMU/L
Type Designation Code M 2 V 56 S
This rule is applied to only Synchronous DRAM family.
4 0 A KT - 5
Speed Grade 5: 166MHz@CL3, 133MHz@CL2 6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2 Package Type KT: STSOP(II) Process Generation A:2nd. gen. Function Reserved for Future Use Organization 2 n 2: x4, 3: x8, 4: x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) Mitsubishi Main Designation
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation
/CS
Input
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
A0-12
Input
BA0,1
Input
DQ0-15
Input / Output Data In and Data out are referenced to the rising edge of CLK.
DQM DQMU/L
Input
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle.
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE X H H L L L BA0,1 X X V V X V A10 /AP X X V L H L A0-9, note 11-12 X X V X X V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA REFA REFS REFSX TBST MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
H X X X X X L
V X X X X X V 1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-9,11-12=L, A0-A6 =Mode Address
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State IDLE /CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 Address Command DESEL NOP TBST NOP NOP ILLEGAL*2 Action
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
WRITE / WRITEA ACT PRE / PREA REFA MRS
Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State WRITE /CS H L L /RAS X H H /CAS X H H /WE X H L X X X Address Command DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, L H L H BA, CA, A10 READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING /CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER SET
MRS
IDLE
REFA
AUTO REFRESH
CKEL
CLK SUSPEND
CKEH ACT
CKEL CKEH
POWER DOWN
TBST WRITE
ROW ACTIVE
TBST READ
CKEL
WRITEA WRITE
READA READ
CKEL
WRITE WRITE SUSPEND CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
WRITEA WRITEA SUSPEND CKEH
CKEL PRE PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE
V
BA0,1 A12-A0
BA0 BA1 A12 A11 A10 A9 0 0 0 0 0 SW
A8 0
A7 0
A6
A5
A4
A3 BT
A2
A1 BL
A0
LTMODE
SW
0 1
Burst Write Single Write
BL 000 001 010 0 1 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1
CL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
/CAS LATENCY R R 2 3 R R R R
BURST LENGTH
LATENCY MODE
BT=0 1 2 4 8 R R R Full Page
BT=1 1 2 4 8 R R R R
BURST TYPE
SEQUENTIAL INTERLEAVED
R: Reserved for Future Use
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
CLK Command Address DQ /CAS Latency CL= 3 BL= 4 Burst Length Burst Type Burst Length
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 1 2 2 3 0 1 3 0 1 0 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-12. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=3)
CLK Command ACT
tRRD
ACT
tRCD
READ
PRE
tRP
ACT
A0-9,11-12
Xa
Xb
Yb
Xa
A10
Xa
Xb
0
1
Xa
BA0-1
00
01
01
00
DQ
Qb0
Qb1
Qb2
Qb3
Precharge All
READ A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A09 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM Multi Bank Interleaving Read (CL=2, BL=4)
CLK Command ACT
tRCD
READ
ACT
tRCD
READ PRE
tRP
ACT
A0-9,11-12
Xa
Ya
Xb
Yb
Xa
A10
Xa
0
Xb
0
0
Xa
BA0-1
00
00
01
01
00
00
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK Command ACT
tRCD
READ
BL tRP
ACT
A0-9,11-12
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
00
DQ
Qa0
Qa1
Qa2
Qa3
i nternal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK Command ACT
tRCD
READ
BL
ACT
DQ
CL=2
Qa0
Qa1
Qa2
Qa3
DQ
CL=3
Qa0
Qa1
Qa2
Qa3
i nternal precharge starts
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SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
WRITE A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4), A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. Write (BL=4)
CLK Command ACT
tRCD
Write
BL
PRE
tRP
ACT
A0-9,11-12
Xa
Ya
Xa
A10
Xa
0
0
Xa
BA0-1
00
00
tWR
00
DQ
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK Command ACT
tRCD
Write
BL tRP
ACT
A0-9,11-12
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
tWR
00
DQ
Da0
Da1
Da2
Da3 internal precharge starts
MITSUBISHI ELECTRIC
17
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read interrupted by Read (CL=2, BL=4)
CLK Command READ READ READ
A0-9,11-12
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
DQ
Qa0
Qa1
Qa2
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read interrupted by Write (CL=2, BL=4)
CLK Command ACT READ Write
A0-9,11-12
Xa
Ya
Ya
A10
Xa
0
0
BA0-1
00
00
00
DQM DQ Qa0 Da0 Da1 Da2 Da3
Output disable by DQM
by WRITE
MITSUBISHI ELECTRIC
18
SDRAM (Rev.1.01) Single Data Rate July '01 [ Read Interrupted by Precharge ]
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Precharge (BL=4)
CLK Command READ PRE
DQ
Q0
Q1
Q2
Command
READ
PRE
CL=2
DQ Q0 Q1
Command
READ PRE
DQ
Q0
Command
READ
PRE
DQ
Q0
Q1
Q2
Command
READ
PRE
CL=3
DQ Q0 Q1
Command
READ PRE
DQ
Q0
MITSUBISHI ELECTRIC
19
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
[ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Terminate (BL=4)
CLK Command READ TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
CL=2
DQ Q0 Q1
Command
READ TBST
DQ
Q0
Command
READ
TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
CL=3
DQ Q0 Q1
Command
READ TBST
DQ
Q0
MITSUBISHI ELECTRIC
20
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write interrupted by Write (BL=4)
CLK Command Write Write Write
A0-9,11-12
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
DQ
Da0
Da1
Da2
Db0
Dc0
Dc1
Dc2
Dc3
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care". Write interrupted by Read (CL=2, BL=4)
CLK Command ACT Write READ
A0-9,11-12
Xa
Ya
Yb
A10
Xa
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
don't care
MITSUBISHI ELECTRIC
21
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. Write interrupted by Precharge (BL=4)
CLK Command ACT Write PRE
tRP
ACT
A0-9,11-12
Xa
Ya
Xa
A10
0
0
0
0
BA0-1
00
00
00
00
DQM
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK. Write interrupted by Terminate (BL=4)
CLK Command ACT Write TBST Write
A0-9,11-12
Xa
Ya
Yb
A10
0
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3
MITSUBISHI ELECTRIC
22
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA interrupted by WRITE to another bank (BL=4)
CLK Command Write Write
BL tRP
ACT
A0-9,11-12
Ya
Yb
t WR
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3
auto-precharge interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK Command Write Read
BL tRP
ACT
A0-9,11-12
Ya
Yb
t WR
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
auto-precharge interrupted
activate
MITSUBISHI ELECTRIC
23
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ] Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA interrupted by READ to another bank (CL=2, BL=4)
CLK Command Read Read
BL tRP
ACT
A0-9,11-12
Ya
Yb
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
auto-precharge interrupted
activate
Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal. Single Write When sigle write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
MITSUBISHI ELECTRIC
24
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an autorefresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command. Auto-Refresh
CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 minimum tRFC
NOP or DESELECT
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
25
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK NOP
/CS /RAS /CAS /WE CKE A0-12 BA0-1
new command X 00
Self Refresh Entry
Self Refresh Exit
minimum tRFC for recovery
MITSUBISHI ELECTRIC
26
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK tIH CKE tIS tIH tIS
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP NOP Standby Power Down
CKE Command
ACT NOP NOP NOP
Active Power Down
DQ Suspend by CKE
CLK CKE Command
Write Read
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
27
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
DQM CONTROL DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0. During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK Command DQMU/L
Write Read
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMU/L=H
disabled by DQMU/L=H
MITSUBISHI ELECTRIC
28
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temprature Storage Tempreture Ta=25'C Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings Unit V V V V mA mW 'C 'C
-0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5
50 1000
0~ 70 -65 ~ 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70C, unless otherwise noted)
Limits Symbol Vdd Vss VddQ VssQ VIH VIL Parameter Min. Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage fo Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 Vdd+0.3 0.8 V V V V V V Unit
CAPACITANCE
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance,address pin Input Capacitance,control pin Input Capacitance,CLK pin Input Capacitance,I/O pin VI=1.4V f=1MHz VI=25mVrms Test Condition Min. 2.5 2.5 2.5 4.0 Max. 3.8 3.8 3.5 6.5 pF pF pF pF Unit
MITSUBISHI ELECTRIC
29
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(max) Symbol Parameter Test Conditions Organi zation x4 Icc1 Operating Current (1bank) tCLK=min, tRC=min, BL=1 x8 x16 Idle Standby Current tCLK=min, CKEVIHmin, /CS>VIHmin tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin, /CS> VIHmin tCLK=L, CKE>VIHmin x4 Icc4 tCLK=min, BL=4, gapless data tCLK=min, tRFC=min CKE<0.2v -5 /-6/-7 x8 x16 Icc5 Icc6 Icc2P Unit Note -5 110 115 120 2 1 30 6 35 15 140 140 150 220 3 -6 90 95 100 1.5 1 25 6 30 15 110 110 120 180 3 -7 80 85 90 1 1 20 6 25 15 90 90 100 170 3 mA mA mA 5 mA 2 mA mA mA mA mA 2,3 2,4 3,5 4,5 mA 1
Notes 1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3xtCLK 4. input signals are stable 5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) IOZ II Parameter
High-Level Output Voltage (DC) Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V, other input pins=0V
Test Conditions
Limits Min. 2.4 0.4 -10 -10 10 10 Max.
Unit V V A A
MITSUBISHI ELECTRIC
30
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V
Limits Symbol Parameter Min. tCLK tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF CLK cycle time CL=2 CL=3 CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time Refresh Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time ACT to ACT Delay time Mode Register Set Cycle time Average Refresh Interval 7.5 6 2.5 2.5 1 1.5 0.8 60 60 15 42 15 12 12 12 7.8 120000 10 -5 Max. Min. 10 7.5 2.5 2.5 1 1.5 0.8 67.5 75 20 45 20 15 15 15 7.8 120000 10 -6 Max. Min. 10 10 3 3 1 2 1 70 80 20 50 20 20 20 20 7.8 120000 10 -7 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Unit Note
CLK
1.4V AC timing is referenced to the input signal crossing through 1.4V.
Signal
1.4V
MITSUBISHI ELECTRIC
31
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits Symbol Parameter Min. CL=2 tAC Access Time from CLK CL=3 CL=2 tOH Output Hold Time from CLK CL=3 tOLZ Delay Time, Output Low impedance from CLK Delay Time, Output High impedannce from CLK CL=2 CL=3 3 0 3 3 5.4 5.4 3 0 3 3 6 5.4 3 0 3 3 6 6 ns ns ns ns 3 5.4 3 5.4 3 6 ns ns -5 Max 5.4 Min. -6 Max 6 Min. -7 Max 6 ns Unit
tOHZ
Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.
Output Load Condition
Vout 50pF
CLK
1.4V
DQ tOLZ tAC tOH tOHZ
1.4V
MITSUBISHI ELECTRIC
32
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Burst Write (Single Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT #0
WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
33
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Burst Write (Multi Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC tRC
/CS
tRAS tRRD tRP
/RAS
tRCD tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
PRE#0
ACT #0
WRITE#0 ACT#1
PRE#0
WRITEA#1 (Auto-Precharge)
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
34
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Burst Read (Single Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP tRAS
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ#0
PRE#0
ACT #0
READ#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
35
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Burst Read (Multi Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC tRC
/CS
tRRD tRAS
/RAS
tRCD tRCD tRCD
/CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READA#0 ACT#1 READA#1
ACT #0
READ#0 ACT #1
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
36
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Write Interrupted by Write [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
0
1
0
0
1
D0
D0
D0
D0
D0
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
WRITE#0 WRITEA #1 interrupt interrupt same other bank bank
WRITE#0 interrupt other bank
PRE#0 ACT #1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
37
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Read Interrupted by Read [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
1
1
0
1
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READ#0 ACT#1
READ#1 interrupt other bank
READA#1
READ#0 ACT #1
interrupt interrupt same bank other bank
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
38
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X X Y Y Y
X
X
X
X
0
1
0
1
1
1
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE#0 ACT#1
READ#1
WRITE#1
PRE#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
39
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Write / Read Terminated by Precharge [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRP tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y X Y X
X
X
X
X
X
X
0
0
0
0
0
0
0
D0
D0
Q0
Q0
ACT#0
WRITE#0
PRE#0 ACT#0 Terminate
READ#0
PRE#0 Terminate
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
40
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y Y Y
X
X
0
0
0
0
0
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0
WRITE#0 TBST
READ#0 TBST
WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
41
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Single Write Burst Read [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y Y
X
X
0
0
0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0
READ#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
42
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Power-Up Sequence and Intialize
CLK
100s
/CS
tRP tRFC tRFC tRSC
/RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
NOP Power On PRE ALL REFA REFA REFA MRS ACT #0
MA
X
0
X
0
X
0
0
Minimum 8 REFA cycles
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
SDRAM (Rev.1.01) Single Data Rate July '01 Auto Refresh
0 1 2 3 4 5
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y
X
X
0
0
D0
D0
D0
D0
PRE ALL
REFA
ACT#0
WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
44
SDRAM (Rev.1.01) Single Data Rate July '01 Self Refresh
0 1 2 3 4 5
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X
X
X
0
PRE ALL Self Refresh Entry All banks must be idle before REFS is issued.
Self Refresh Exit
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
45
SDRAM (Rev.1.01) Single Data Rate July '01 CLK Suspension [CL=2, BL=4]
0 1 2 3 4 5
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
6
7
8
9
10
11
12
13
14
15
16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X Y Y
X
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 internal CLK suspended
READ#0
internal CLK suspended
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
46
SDRAM (Rev.1.01) Single Data Rate July '01 Power Down
0 1 2 3 4 5
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
6
7
8
9
10
11
12
13
14
15
16
CLK /CS /RAS /CAS /WE
Standby Power Down Active Power Down
CKE DQM A0-9,11 A10 A12 BA0,1 DQ
X
X
X
0
PRE ALL
ACT #0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
47
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customerOs application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-partyOs rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corp oration or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
48
SDRAM (Rev.1.01) Single Data Rate July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Revison History
Rev. Date Description
1.01
July / '01 1st edition
MITSUBISHI ELECTRIC
49

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